Methods and devices for determining writing current for memory cells

ABSTRACT

Methods for determining writing current for memory cells. A first reference current is applied to a first operative line to switch the memory cell to a first state. A second reference current is applied to a second operative line crossing the first operative line to switch the memory cell to a second state. A first writing current is obtained according to a first ratio and the first reference current. A second writing current is obtained according to a second ratio and the second reference current. The memory cell is programmed by applying the first writing current to the first operative line and applying the second writing current to the second operative line.

BACKGROUND

The disclosure relates in general to Magnetoresistive Random AccessMemory (MRAMs), and more particularly to methods and devices todeterminate writing current for MRAM cells.

Magnetic random access memory (MRAM) cells are often based on a magnetictunnel junction (MTJ) cell. Basically, an MTJ configuration can be madeup of three basic layers, a “free” ferromagnetic layer (free layer), aninsulating tunneling barrier, and a “pinned” ferromagnetic layer (pinnedlayer). In the free layer, the magnetization moments are free to rotateunder an external magnetic field, but the magnetic moments in the“pinned” layer cannot. The pinned layer can be composed of aferromagnetic layer and/or an anti-ferromagnetic layer which “pins” themagnetic moments in the ferromagnetic layer. A very thin insulationlayer forms the tunneling barrier between the pinned and free magneticlayers. In order to detect states in the MTJ configuration, a constantcurrent can be applied through the cell. As the magneto-resistancevaries according to the state stored in the cell, the voltage can bedetected over the memory cell. To write or change the state of thememory cell, an external magnetic field can be applied, sufficient tocompletely switch the direction of the magnetic moments of the freemagnetic layers.

MTJ configurations often employ the Tunneling Magneto-Resistance (TMR)effect, which allows magnetic moments to quickly switch the directionsin the magnetic layer by an application of an external magnetic field.Magneto-resistance (MR) is a measure of the ease with which electronsflow through the free layer, tunneling barrier, and the pinned layer. Aminimum MR occurs in an MTJ configuration when the magnetic moments inboth magnetic layers have the same direction or are “parallel”. Amaximum MR occurs when the magnetic moments of both magnetic layers arein opposite directions or are “anti-parallel.”

FIG. 1A is a schematic perspective view illustrating a conventional MTJmemory cell of an MRAM device. FIG. 1B is a schematic perspective viewillustrative of read out operation of the MTJ memory cell of FIG. 1A.FIG. 1C is a plane view illustrative of respective magnetization statesdepending on stored data of the MTJ memory cell of FIG. 1A.

A single memory cell comprises first operative layer 11, pinned layer12, tunnel barrier layer 13, free layer 14, and second operative layer12. The MTJ memory cell comprises pinned layer 12, dielectric layer 13,and free layer 14. The tunnel barrier layer 13 is sandwiched betweenpinned layer 12 and free layer 14. The pinned layer 12 is in contactwith the first operative layer 11. The free layer 14 is in contact withthe second operative layer 12. The pinned layer 12 and the free layer 14are ferromagnetic materials. The dielectric layer 13 is an insulatingmaterial. The pinned layer 12 has a fixed magnetization direction. Thedielectric layer 13 has a thickness of about 1.5 nanometers. The freelayer 14 has a thickness of about 20 nanometers. The free layer 14 has afreely changeable magnetization direction.

The magnetization direction of the free layer 14 indicates stored data.The free layer 14 serves as a data storage layer. The first operativelayer 11 and the second operative layer 15 extend in directionsperpendicular to each other. The MTJ memory cell is positioned at acrossing point between the first operative layer 11 and the secondoperative layer 15. In FIG. 1B, a current 16 flows from the firstoperative layer 11 to the second operative layer 15 through the pinnedlayer 12, the dielectric layer 13, and the free layer 14. The MTJ memorycell is capable of storing binary digit data “0” and “1”. If themagnetization directions of the pinned layer 12 and the free layer 14are parallel to each other, the MTJ memory cell stores a first binarydigit, for example, “0”. If the magnetization directions of the pinnedlayer 12 and the free layer 14 are not parallel, the MTJ memory cellstores a second binary digit, for example, “1”. The magnetizationdirection of the free layer 14 changes depending on an externallyapplied magnetic field.

Electrical resistance of the dielectric layer 13 varies by about 10-60%due to tunneling magnetoresistance effect between a first state wherethe magnetization directions of the pinned layer 12 and the free layer14 are parallel and a second state where the magnetization directions ofthe pinned layer 12 and the free layer 14 are not parallel. Apredetermined potential difference or a predetermined voltage is appliedto the first and second operative layers 11 and 15 to apply a tunnelingcurrent from the pinned layer 12 to the free layer 14 through thedielectric layer 13. This tunneling current varies depending on thevariable electrical resistance of the dielectric layer 13 due totunneling magnetoresistance. Data can be retrieved from the MTJ memorycell by detecting the variation in the tunneling current.

FIG. 2A is a fragmentary schematic perspective view illustrative of anarray of MTJ memory cells. FIG. 2B is a fragmentary schematicperspective view illustrative of the array of the MTJ memory cellsduring the operation shown in FIG. 2A.

The first operative layers 11 extend parallel to each other in a firstdirection. The second operative layers 15 extend parallel to each otherin a second direction, perpendicular to the first direction. The singlefirst operative layer 11 and the single second operative layer 15 have asingle crossing point, where a single MTJ memory cell “C” is provided.The first operative layers 11 and the second operative layers 15 have anarray of crossing points where plural MTJ memory cells “C” are provided.The first operative layers 11 serve as word lines. The second operativelayers 15 serve as bit lines. One of the plural MTJ memory cells “C” isselected by selecting one of the word lines and one of the bit lines,for read or write operations to the selected MTJ memory cell “C”.

The MRAM has the array of the MTJ memory cells, each of which comprisesthe tunneling magnetoresistance element utilizing the tunnelingmagnetoresistance effect, wherein the tunneling magnetoresistanceelement includes an insulating thin film sandwiched between the two ormore ferromagnetic thin films. The tunneling magnetoresistance elementis switched between a first state, in which the magnetization directionsof the two ferromagnetic thin films are parallel to each other, and asecond state, in which the magnetization directions of the twoferromagnetic thin films are anti-parallel. The resistance of theinsulating film, detected the tunneling current, is different for thefirst and second states. These two states correspond to binary digits,for example, the first state can correspond to data “0”, and the secondstate to data “1”.

The write operation is accomplished as follows. One of the word lines 11and one of the bit lines 15 are selected. A first write current Isw isapplied to the selected word line 11 s. A first magnetic field Msw isgenerated around the selected word line 11 s. The first write currentIsw has a predetermined current value and a predetermined direction. Asecond write current Isb is applied to the selected bit line 15 s. Thesecond write current Isb has a predetermined current value and apredetermined direction. A second magnetic field Msb is generated aroundthe selected bit line 15 s. As a result, a superimposed magnetic fieldof both the first and second magnetic field Msw and Msb is applied tothe crossing point of the selected word line 11 s and the selected bitline 15 s. The selected MTJ memory cell “Cs” is positioned at thecrossing point of the selected word line 11 s and the selected bit line15 s, for which reason the selected MTJ memory cell “Cs” is applied withthe superimposed magnetic field. The free layer of the selected MTJmemory cell “Cs” is also applied with the superimposed magnetic field,whereby magnetic domains of the free layer become ordered in a firstdirection, for example, parallel to the magnetization direction of thepinned layer. As a result, the selected MTJ memory cell “Cs” stores abinary digit data “0”.

Any first write current Isw or second write current Isb changes itscurrent direction to an opposite direction, whereby the direction of themagnetic field is inverted, and the direction of the superimposedmagnetic field is changed by approximately 90 degrees. As a result, themagnetic domains of the free layer become ordered in a second direction,for example, in a direction anti-parallel to the magnetization directionof the pinned layer. As a result, the selected MTJ memory cell “Cs”stores another binary digit “1”.

The read operation is accomplished as follows. One of the word lines 11and one of the bit lines 15 are selected. A potential difference isapplied between the selected word line 11 s and the selected bit line 15s for measuring a current value to detect a resistance value of theselected memory cell “Cs” to the tunneling current. Namely, apredetermined potential difference or a predetermined voltage is appliedto the selected word line 11 s and the selected bit line 15 s to providea tunneling current from the pinned layer through the insulating layerto the free layer of the selected memory cell “Cs”. This tunnelingcurrent varies depending on the variable electrical resistance of theinsulating layer due to the tunneling magnetoresistance effect. Thebinary digit data can be detected from the selected memory cell “Cs” bydetecting the variation in the tunneling current.

As described, the ability of this type of cell to store electricallyaccessible data hinges on electron tunneling between the free layer andthe pinned layer, which in turn is dependent on the relative directionsof magnetization of these two regions. Rotating the magnetization in thefree layer into one of at least two selectable directions results inbinary state stored in the cell. If the cell is oriented with itsmagnetic easy-axis (“EA”) horizontal, an electrical writing currentthrough a vertical line will apply an EA magnetic field, and a currentthrough a horizontal line will apply a hard-axis (“HA”) magnetic field,to the cell.

In one implementation of MRAM cells, the writing of individual cellsadheres to a concept referred to as the “asteroid” for switching. Theswitching threshold of a single free region depends on the combinationof EA and HA magnetic fields applied thereto. This “Stoner-Wohlfarth”asteroid model, shown in FIG. 3A, illustrates these threshold values inthe plane of applied EA and HA fields. Switching occurs when acombination of EA and HA fields at the cell results in a vector outsideof the asteroid curve. Vectors inside the asteroid curve will not switchthe cell from one of its current bi-stable states. This asteroid modelalso illustrates how the EA field needed to switch a device is reducedin the presence of an HA bias field. Selectively switching a single cellwithin the array is achieved by applying electrical currents through aselected pair of horizontal and vertical lines. These currents generatea combination of EA and HA fields only at the cell located at theintersection of these lines, theoretically switching the selected cell,but not the neighboring cells.

All the cells along the horizontal line experience the same applied HAfield. Similarly all the cells along the vertical line experience thesame applied EA field. However, only the cell at the intersection ofthese lines experiences the combination of both fields necessary forswitching.

Problems arise when the thresholds of the asteroid curve vary from cellto cell, and from hysteresis loop to hysteresis loop in the same cell.This leads to a broadening of the asteroid into a band of thresholdvalues as shown in FIG. 3B. Since the ability to selectively switchcells hinges on all cells except one along a line not being switchedunder a single applied HA or EA field, if this band of the asteroidcurve broadens excessively, it is no longer possible to selectivelywrite individual cells, with equivalent writing stimuli, since othernon-selected cells along the lines will also switch. In other words, ifthe magnetic field generated by writing lines is too weak or theswitching field for the magnetoresistive cell is too large, writingoperation cannot be successful. In addition, if the magnetic fieldgenerated by writing lines is too strong or the switching field for themagnetoresistive cell is too small, writing disturb occurs on theon-wanted cells.

Whether using the above-discussed asteroid selection model, or any otherselection model, a major challenge in the successful implementation ofan MRAM array with effective cell selectivity is the fabrication of manymemory cells with nearly identical electrical and magnetic properties.This is particularly difficult for magnetic devices since their responseis sensitive not only to local defects but also to edge or surfaceroughness.

SUMMARY

Methods and devices for determining writing current for memory cells areprovided. An embodiment of the memory device comprises: a firstoperative line; a memory cell; a writing adjustment unit operative togenerate a first parameter representing a first ratio of a firstreference current, and generate an initial signal; and a program/erasecontrol unit operative to switch the memory cell to a second state inresponse to the initial signal, provide the first reference current tothe first operative line to switch the memory cell to a first state, andprovide a first writing current according to the first ratio and thefirst reference current to the first operative line to switch the memorycell to the first state or the second state.

An embodiment of an MRAM memory device comprises: an MRAM arraycomprising a plurality of first operative lines, a plurality of secondoperative lines crossing the first operative lines, a plurality of-magnetic tunnel junction memories, each of the plurality of magnetictunnel junction memories comprising a pinned layer, a free layer, and anon-magnetic layer located between the pinned layer and the free layer,and being positioned at a crossing point of the first operative line andthe second operative line; a writing adjustment unit operative togenerate a first parameter representing a first ratio of a firstreference current and a second parameter representing a second ratio ofa second reference current, and generate an initial signal beforegenerating the first reference current and the second reference current;and a program/erase control unit operative to switch the magnetic tunneljunction memory to a second state in response to the initial signal,provide the first reference current to the first operative line togenerate a first magnetic field to switch the magnetic tunnel junctionmemory to a first state, provide the second reference current to thesecond operative line to generate a second magnetic field to switch themagnetic tunnel junction memory to the first state, provide a firstwriting current according to the first ratio and the first referencecurrent to the first operative line, and provide a second writingcurrent according to the second ratio and the second reference currentto the second operative line to switch the magnetic tunnel junctionmemory to the first state or the second state.

An embodiment of a method for determining writing current for memorycells comprises: applying a first reference current to a first operativeline to switch the memory cell to a first state; applying a secondreference current to a second operative line crossing the firstoperative line to switch the memory cell to a second state; obtaining afirst writing current according to a first ratio and the first referencecurrent; obtaining a second writing current according to a second ratioand the second reference current; and programming the memory cell byapplying the first writing current to the first operative line andapplying the second writing current to the second operative line.

Another embodiment of a method for determining writing current formemory cells comprises: applying a first reference current to a firstoperative line to switch the memory cell to a first state; applying asecond reference current to a second operative line crossing the firstoperative line to switch the memory cell to a second state; obtaining afirst writing current according to a first ratio and the first referencecurrent; obtaining a second writing current according to a second ratioand the second reference current; and programming the memory cell byapplying the first writing current to the first operative line andapplying the second writing current to the second operative line.

DESCRIPTION OF THE DRAWINGS

The invention will become more fully understood from the detaileddescription, given hereinbelow, and the accompanying drawings. Thedrawings and description are provided for purposes of illustration onlyand, thus, are not intended to be limiting of the present invention.

FIG. 1A is a schematic perspective view illustrative of a conventionalMTJ memory cell of an MRAM device.

FIG. 1B is a schematic perspective view illustrative of a read outoperation of the MTJ memory cell of FIG. 1A.

FIG. 1C is a plan view illustrative of respective magnetization statesdepending on stored data of the MTJ memory cell of FIG. 1A.

FIG. 2A is a fragmentary schematic perspective view illustrative of anarray of MTJ memory cells of the MRAM of FIG. 1A.

FIG. 2B is a fragmentary schematic perspective view illustrative of thearray of the MTJ memory cells during a write operation shown in FIG. 2A.

FIG. 3A is an “asteroid” model of the magnetic response of a single,ideal magnetic tunnel junction.

FIG. 3B is an “asteroid” model of the magnetic response of singlemagnetic tunnel junction cells, each cell having an unpredictableresponse narrowing the operating window of electrical and magneticstimuli values able to effectively operate an array of such cells.

FIG. 4 is a schematic perspective view illustrative of one memory cellof the MRAM device.

FIG. 5 is a flowchart of an embodiment of a method for determining firstand second magnetic fields Msw and Msb for writing memory cells.

FIG. 6 is an asteroid model of the magnetic response of an MTJ memorycell 40 using the method described in FIG. 5.

FIG. 7 is a flowchart of another embodiment of a method for determiningfirst and second magnetic fields Msw and Msb for writing memory cells.

FIG. 8 is a schematic diagram of an embodiment of an MRAM memory device.

FIG. 9 is a schematic diagram of an embodiment of the MRAM array 71.

DETAILED DESCRIPTION

FIG. 4 is a schematic perspective view illustrative of one memory cellof the MRAM device. The memory cell comprises a first operative layer41, an MTJ memory cell 40, and a second operative layer 45. The MTJmemory cell 40 comprises the pinned layer 42, the dielectric layer 43,and the free layer 44. The tunnel barrier layer 43 is sandwiched betweenthe pinned layer 42 and the free layer 44. The pinned layer 42 is incontact with the first operative layer 41. Here, the first and secondoperative layers may comprise metal, metal alloy, metal compound,silicon or silicide, and the first operative layer 41 can be coupled orisolated with the MTJ memory cell 40 in different implementations.

The pinned layer 42 and the free layer 44 are of ferromagneticmaterials. The tunnel barrier layer 43 is made of an insulatingmaterial. The pinned layer 42 has a fixed magnetization direction. Thedielectric layer 43 has a thickness of about 1.5 nanometers. The freelayer 44 has a thickness of about 20 nanometers. The free layer 44 has afreely changeable magnetization direction.

The magnetization direction of the free layer 44 indicates stored data.The free layer 44 serves as a data storage layer. The first operativelayer 41 and the second operative layer 45 extend in directionssubstantially perpendicular to each other. The MTJ memory cell 40 ispositioned at a crossing point between the first operative layer 41 andthe second operative layer 45. The MTJ memory cell 40 is capable ofstoring binary digit data “0” and “1”. If the magnetization directionsof the pinned layer 42 and the free layer 44 are parallel to each other,then the MTJ memory cell 40 stores a first binary digit, for example,data “0”. If the magnetization directions of the pinned layer 42 and thefree layer 44 are not parallel, the MTJ memory cell 40 stores a secondbinary digit, for example, “1”. The magnetization direction of the freelayer 44 is changed depending on an externally applied magnetic field.

Electrical resistance of the dielectric layer 43 varies by about 10-300%due to tunneling magnetoresistance between a first state, where themagnetization directions of the pinned layer 42 and the free layer 44are parallel, and a second state, where the magnetization directions ofthe pinned layer 42 and the free layer 44 are anti-parallel. Apredetermined potential difference or a predetermined voltage is appliedto the first and second operative layers 41 and 45 to provide atunneling current from the pinned layer 42 to the free layer 44 throughthe dielectric layer 43. This tunneling current varies depending on thevariable electrical resistance of the dielectric layer 43 due totunneling magnetoresistance effect. The data can be retrieved from theMTJ memory cell 40 by detecting the variation in the tunneling current.

During a write operation, the first operative line (word line) 41 andthe second operative line (bit line) 45 are selected. A first writecurrent Isw is applied to the selected word line 41. A first magneticfield Msw is generated around the selected word line 41. The first writecurrent Isw has a predetermined current value and a predetermineddirection. A second write current Isb is applied to the selected bitline 45. The second write current Isb has a predetermined current valueand a predetermined direction. A second magnetic field Msb is generatedaround the selected bit line 45. As a result, a superimposed magneticfield of both the first and second magnetic fields Msw and Msb isapplied to the crossing point of the selected word line 41 and theselected bit line 45. The selected MTJ memory cell 40 is positioned atthe crossing point of the selected word line 41 and the selected bitline 45, for which reason the superimposed magnetic field is applied tothe selected MTJ memory cell 40. The free layer of the selected MTJmemory cell 40 is also subjected to the superimposed magnetic field,whereby magnetic domains of the free layer become ordered in a firstdirection, for example, parallel to the magnetization direction of thepinned layer. As a result, the selected MTJ memory cell 40 stores abinary digit data “0”.

FIG. 3A is an asteroid model of the magnetic response of a single, idealmagnetic tunnel junction. As described in FIGS. 3A and 3B, problemsarise when the thresholds of the asteroid vary from cell to cell, andfrom hysteresis loop to hysteresis loop in the same cell, leading to abroadening of the asteroid into a band of threshold values. In addition,the changed operating environment, or process variation also change therange of the asteroid. Since switching of the memory cell occurs when acombination of EA and HA fields at the cell results in a vector outsideof the asteroid, and vectors inside the asteroid do not switch the cellfrom one of its current bi-stable states, it is important to determine aproper first and second magnetic fields Msw and Msb for writing memorycells.

FIG. 5 is a flowchart of an embodiment of a method for determining thefirst and second magnetic fields Msw and Msb for writing memory cells,using the MTJ memory cell 40 shown in FIG. 4 as an example.

An initial state of the MTJ memory cell 40 is set up (S1), for example,a strong reverse current applied to the first operative line 41 or thesecond operative line 45, or both, to erase-or program the MTJ memorycell 40 to store a predetermined state, “0” as an example. Note that themagnetic field generated by the current in step S1 is strong enough toswitch the resistive state of the MTJ memory cell 40.

Next, a first testing current is increasingly applied to first operativeline 41 only until resistance of MTJ memory cell 40 is switched toanother state, “1” as an example, thus a first reference current I1 isobtained (S2). Next, the predetermined state “0” of the MTJ memory cell40 is set up again by applying the strong reverse current as describedin step S1 (S3). Next, a second testing current is increasingly appliedto second operative line 45 only until resistance of MTJ memory cell 40is switched to state “1”, thus a second reference current I2 is obtained(S4). Note that the magnetic field generated by first reference currentI1 or second reference current I2 can switch the resistance of the MTJmemory cell 40 individually.

Next, ratios of the first reference current I1 and the second referencecurrent I2 are determined (S5). The range of the ratio may be between20%˜80%, preferably 50%. Next, a first writing current I3 is setaccording to the ratio belonging to first reference current I1 and firstreference current I1, and a second writing current I4 is set accordingto the ratio belonging to second reference current I2 and secondreference current I2 (S6), for example, first writing current I3 can bea ratio of first reference current I1, and second writing current I4 canbe a ratio of the second reference current I2. Note that the ratio ofthe first reference current I1 and the second reference current I2 canbe different values or the same, depending on real implementations.

Next, the reference currents I1 and I2 and writing currents I3 and I4are recorded as the parameters for writing the MTJ memory cell 40 inwriting operation (S7).

FIG. 6 is an asteroid model of the magnetic response of the MTJ memorycell 40 using the method described in FIG. 5. As-shown in FIG. 6, theratios of the reference currents I1 and I2 are set as 50%, thus firstwriting current I3 and second writing current I4 are both half ofreference currents I1 and I2, respectively. The magnetic fieldsgenerated by first writing current I3 and second writing current I4define an operating point A, outside the asteroid, thus the resistanceof the MTJ memory cell is switched by the magnetic fields generated byfirst writing current I3 and second writing current I4 successively.

FIG. 7 is a flowchart of another embodiment of a method for determiningthe first and second magnetic fields Msw and Msb for writing memorycells, using the MTJ memory cell 40 shown in FIG. 4 as an example.

An initial state of the MTJ memory cell 40 is set up (S11), for example,a strong reverse current applied to the first operative line 41 or thesecond operative line 45, or both, to erase or program the MTJ memorycell 40 to store a predetermined state, “0” as an example. Note that themagnetic field generated by the current in step S1 is strong enough toswitch the resistive state of the MTJ memory cell 40.

Next, a first testing current is increasingly applied to first operativeline 41 only until resistance of MTJ memory cell 40 is switched toanother state, “1” as an example, thus a first reference current I1 isobtained (S12). Next, a second testing current is increasingly appliedto second operative line 45 only until resistance of MTJ memory cell 40is switched to state “0”, thus a second reference current I2 is obtained(S13).

Next, ratios of the first reference current I1 and the second referencecurrent I2 are determined (S14). The range of the ratio may be between20%˜80%, preferably 50%. Next, a first writing current I3 is setaccording to the ratio belonging to first reference current I1 and firstreference current I1, and a second writing current I4 is set accordingto the ratio belonging to second reference current I2 and secondreference current I2 (S15), for example, first writing current I3 can bea ratio of first reference current I1, and second writing current I4 canbe a ratio of the second reference current I2. Note that the ratio ofthe first reference current I1 and the second reference current I2 canbe different values or the same, depending on real implementations.

Next, the reference currents I1 and I2 and writing currents I3 and I4are recorded as the parameters for writing the MTJ memory cell 40 inwriting operation (S16).

FIG. 8 is a schematic diagram of an embodiment of an MRAM memory device.The MRAM memory device 70 comprises an MRAM array 71, a writingadjustment unit 73, a program/erase control unit 75, and a storage unit77. While FIG. 8 shows only a memory array, the MRAM memory device 70may select predetermined bits of memory cells in a die, a memory bank,or a memory array for determination of operation point for memorywriting operation.

FIG. 9 is a schematic diagram of an embodiment of the MRAM array 71. Aselected MTJ memory cell 80A is written by passing current Isw throughfirst operative line 82A, and current Isb through second operative line84A. According to the asteroid curve, the magnetic field produced byeither Isw or Isb alone in the region of the MTJ memory cells is lessthan the magnetic field required to change the magnetic state in an MTJmemory cell, thus, half-selected MTJ memory cells 80B (those over whichonly Isw or Isb alone is passing) are not written. The combination ofmagnetic fields from Isw and Isb is, however, sufficient to change thestate of selected MTJ memory cell 80A.

In a read operation, a forward bias voltage is established across theselected MTJ memory cell 80A by pulling the second operative line 84Avoltage down, and raising the first operative line 82A voltage. Inaddition, unselected first operative lines 82B and second operativelines 84B remain at standby voltages, thus, half-selected MTJ memorycells have a zero voltage drop from second operative line to firstoperative line and do not conduct.

In FIG. 8, program/erase control unit 75 increasingly provides a firsttesting current to the first operative line until resistance of theselect MTJ memory cell is switched, to obtain a first reference current.In addition, program/erase control unit 75 increasingly provides asecond testing current to the second operative line until resistance ofthe select MTJ memory cell is switched, to obtain a second referencecurrent. In an embodiment, an initial state of the selected MTJ memorycell is set up before providing the first testing current and the secondtesting current by applying a magnetic field strong enough, to switchthe resistive state of the select MTJ memory cell to store apredetermined state, “0” as an example. In another embodiment, theinitial state of the selected MTJ memory cell is only set up beforeproviding the first testing current applying the magnetic field strongenough to switch the resistive state of the select MTJ memory cell tostore the predetermined state “0”, and the second testing current is theincreasingly applied to the second operative line until resistance ofthe select MTJ memory cell switched form “0” to “1”. In addition, eachmagnetic field generated by first reference current or second referencecurrent switches the resistance of the MTJ memory cell individually.

The writing adjustment unit 73 determines ratios respectively of thefirst reference current and the second reference current. The range ofthe ratios may be between 20%˜80%, 50% as an example. Thus, a firstwriting current is obtained according to the ratio and the firstreference current, and a second writing current is obtained according tothe ratio and the second reference current. The parameters indicatingthe ratios, the first reference current and the second referencecurrent, and the first writing current and the second writing current,can be stored in storage unit 77, which can be an individual memory or apart of the MRAM array 71.

Thus, during writing operation, program/erase control unit 75 providesthe first writing current to the first operative line, and the secondwriting current to the second operative line to program the selected MTJmemory cell.

In an embodiment, testing current is only applied to one operative linefor the adjustment of the writing magnetic field generated by thisoperative line, and the writing magnetic field generated by anotheroperative line of the memory cell can be a fixed value.

In an embodiment, the method for determining writing current accordingto embodiments of the invention can be implemented before the memorydevice leaves the factory, automatically implemented in a predeterminedperiod, or by user, to achieve a reliable nominal value.

In some embodiments, the method for determining writing currentaccording to embodiments of the invention also can be implemented tomemory cells programmed using applied energy, such as parameter RAMs(PRAM) or Ovonic Unified Memories (OUM).

The foregoing description of several embodiments have been presented forthe purpose of illustration and description. Obvious modifications orvariations are possible in light of the above teaching. The embodimentswere chosen and described to provide the best illustration of theprinciples of this invention and its practical application to therebyenable those skilled in the art to utilize the invention in variousembodiments and with various modifications as are suited to theparticular use contemplated. All such modifications and variations arewithin the scope of the present invention as determined by the appendedclaims when interpreted in accordance with the breadth to which they arefairly, legally, and equitably entitled.

1. A memory device, comprising: a first operative line; a memory cell; awriting adjustment unit operative to generate a first parameterrepresenting a first ratio of a first reference current, and generate aninitial signal; and a program/erase control unit operative to switch thememory cell to a second state in response to the initial signal, providethe first reference current to the first operative line to switch thememory cell to a first state, and provide a first writing currentaccording to the first ratio and the first reference current to thefirst operative line to switch the memory cell to the first state or thesecond state.
 2. The memory device as claimed in claim 1, wherein thewriting adjustment unit generates the initial signal before generatingthe first reference current.
 3. The memory device as claimed in claim 1,further comprising a second operative line crossing the first operativeline.
 4. The memory device as claimed in claim 3, wherein the memorycell is positioned at a crossing point of the first operative line andthe second operative line.
 5. The memory device as claimed in claim 1,wherein the memory cell is a magnetic tunnel junction cell.
 6. Thememory device as claimed in claim 5, wherein the first reference currentgenerates a first magnetic field to switch the memory cell to the firststate.
 7. The memory device as claimed in claim 1, further comprising astorage unit operative to store the first parameter.
 8. The memorydevice as claimed in claim 1, wherein the first writing current is thefirst ratio of the first reference current.
 9. The memory device asclaimed in claim 6, wherein the writing adjustment unit is furtheroperative to generate a second parameter representing a second ratio ofa second reference current.
 10. The memory device as claimed in claim 9,wherein the writing adjustment unit is further operative to generate theinitial signal before generating the second reference current.
 11. Thememory device as claimed in claim 9, wherein the program/erase controlunit is further operative to provide the second reference current to thesecond operative line to generate a second magnetic field to switch thememory cell to the first state or the second state, and provide a secondwriting current according to the second ratio and the second referencecurrent to the second operative line to switch the memory cell to thesecond state or the first state.
 12. The memory device as claimed inclaim 9, wherein the storage unit is further operative to store thefirst parameter and the second parameter.
 13. The memory device asclaimed in claim 9, wherein the first writing current is the first ratioof the first reference current and the second writing current is thesecond ratio of the second reference current.
 14. The memory device asclaimed in claim 9, wherein the first ratio and the second ratio arewithin a range of 20%˜80%.
 15. A method for determining writing currentfor memory cells, comprising: applying a first reference current to afirst operative line to switch the memory cell to a first state;applying a second reference current to a second operative line crossingthe first operative line to switch the memory cell to a second state;obtaining a first writing current according to a first ratio and thefirst reference current; obtaining a second writing current according toa second ratio and the second reference current; and programming thememory cell by applying the first writing current to the first operativeline and applying the second writing current to the second operativeline.
 16. The method as claimed in claim 15, further comprising erasingthe memory cell to the second state before applying the first referencecurrent to the first operative line.
 17. The method as claimed in claim15, wherein the first reference current is obtained by increasinglyapplying a first testing current until a state of the memory cell isswitched.
 18. The method as claimed in claim 15, wherein the secondreference current is obtained by increasingly applying a second testingcurrent until a state of the memory cell is switched.
 19. The method asclaimed in claim 15, wherein the memory cell is positioned at a crossingpoint of the first operative line and the second operative line.
 20. Themethod as claimed in claim 15, wherein the memory cell is a magnetictunnel junction cell.
 21. The method as claimed in claim 15, furthercomprising generating a first parameter representing the first ratio ofthe first reference current and a second parameter representing thesecond ratio of the second reference current.
 22. The method as claimedin claim 21, further comprising recording the first parameter and thesecond parameter.